How the switch is realised: conduction physics, capacitance, leakage and package parasitics — and why SiC and GaN changed the answer.
A converter schematic contains ideal switches. Silicon does not. The bridge between the two is the question Erickson and Maksimović put at the centre of switch realization: in which quadrants of the \(( v,\, i )\) plane must this switch operate? The topology answers that, and the answer narrows the device choice before any datasheet is opened.
Conducts one polarity of current, blocks one polarity of voltage. A bare transistor does it. The buck, boost and forward converters need nothing more — the passive switch is a diode.
Conducts either polarity, blocks one. A MOSFET gives this for free: the body diode is the antiparallel path. Every voltage-source inverter leg and every synchronous rectifier lives here.
Conducts one polarity, blocks either. Needs a series diode — which is why current-source inverters and thyristor rectifiers use devices that are poor at reverse blocking on their own.
A synchronous rectifier is worth naming separately: it is a current-bidirectional switch used as the passive switch, replacing a diode drop with \(I \cdot R_{DS(on)}\). That substitution only pays while the on-state resistance stays below the diode's forward voltage divided by the current — which is exactly the trade-off the rest of this page is about.
A power device blocks voltage across a lightly doped drift region. There are only two ways to make that region conduct, and everything else about a device family follows from which one it uses.
In a MOSFET, HEMT or Schottky diode only majority carriers move. The drift region behaves as a resistor, so the on-state is a straight line through the origin:
That positive temperature coefficient is a feature, not a defect: a device that heats up takes less current, so paralleled dice share without external ballasting. The price is that \(R_{DS(on)}\) rises steeply with the required blocking voltage — the subject of the unipolar limit below.
A PiN diode, BJT or IGBT floods its drift region with injected minority carriers. The region's resistivity collapses, and the on-state becomes a junction offset plus a small residual resistance:
This is almost independent of blocking voltage, which is why IGBTs still own 3.3 kV and above. The charge that buys the low on-state has to be removed before the device can block again:
\(\tau\) is the minority-carrier lifetime. Short it (lifetime killing, irradiation) and switching gets faster while the on-state voltage rises. That single knob is the entire bipolar speed-versus-conduction trade-off.
When a diode is commutated off at a rate \(di/dt\), the stored charge appears as reverse current. The peak and the recovered charge are tied together by the commutation slope:
\(E_{rr}\) is dissipated in the opposing transistor as extra turn-on loss, on top of its own overlap loss, and \(Q_{rr}\) itself grows with temperature and with \(di/dt\). A SiC Schottky diode has no stored charge: its reverse current is only displacement current into \(C_j\), essentially independent of temperature.
The off state is not free either. Reverse leakage is set by the intrinsic carrier concentration, and that depends exponentially on the bandgap — the property that actually separates wide-bandgap material from silicon.
Silicon's \(E_g\) is 1.12 eV; 4H-SiC is 3.26 eV and GaN 3.4 eV. At room temperature that is more than ten orders of magnitude in \(n_i\). Blocking loss \(P_{off} = V_{DC} I_{leak}\) is usually negligible — until it is not, because leakage rises faster with temperature than the package can remove heat:
For a one-dimensional non-punch-through drift region held off at breakdown, the specific on-resistance has a closed form — Baliga's unipolar limit:
\(\varepsilon_s\) is the permittivity, \(\mu_n\) the electron mobility and \(E_c\) the critical field for avalanche. \(E_c\) enters cubed, so a material with eight times the critical field buys roughly five hundred times the figure of merit — the same blocking voltage held off by a drift region an order of magnitude thinner and far more heavily doped. Empirically the limit tracks \(R_{on,sp} \propto V_{BR}^{2.4\text{–}2.5}\).
| Property | Si | 4H-SiC | GaN |
|---|---|---|---|
| Bandgap Eg (eV) | 1.12 | 3.26 | 3.40 |
| Critical field Ec (MV/cm) | ≈0.3 | ≈2.5 | ≈3.3 |
| Electron mobility µn (cm²/V·s) | 1400 | ≈950 | ≈1500 (2DEG ≫) |
| Saturation velocity vsat (107 cm/s) | 1.0 | 2.0 | 2.5 |
| Thermal conductivity (W/cm·K) | 1.5 | 3.7–4.9 | 1.3 (GaN-on-Si lower) |
| Commercial structure | vertical, superjunction | vertical (DMOS / trench) | lateral HEMT |
| Reverse conduction | body diode (slow, Qrr) | body diode (fast, low Qrr) | 2DEG, no junction — high VSD |
Structure is not decoration. Where the terminals sit relative to the depletion region decides how large each parasitic capacitance is, how nonlinear it is, and whether the device has a body diode at all.
Every inter-terminal capacitance in a power device is a junction capacitance, so it varies strongly with the voltage across it:
Datasheets publish terminal combinations rather than the physical elements:
Because \(C_{oss}\) is voltage-dependent, the charge stored in it and the energy stored in it are different integrals, and neither equals \(\tfrac{1}{2}C_{oss}V^2\) at a single quoted capacitance:
This is why vendors publish two "equivalent" capacitances — a charge-equivalent \(C_{o(er)}\) and an energy-equivalent \(C_{o(tr)}\) — and why substituting one for the other quietly corrupts a ZVS dead-time calculation. Store the curve, integrate what you actually need.
Driving the gate costs real power, and during the voltage transition the entire gate current goes into \(C_{gd}\) — which is what sets \(dv/dt\):
SiC MOSFETs show \(V_{th}\) hysteresis and bias-temperature instability from interface traps at the SiC/SiO₂ boundary. A threshold measured after a positive gate sweep is not the one the device shows in circuit — which is why the measurement condition has to be recorded with the number.
A SiC body diode conducts at 3–4 V and carries little stored charge. A GaN HEMT has no body diode at all: reverse current flows in the 2DEG once \(V_{SD}\) exceeds roughly \(V_{th} + I R\), so dead-time loss dominates and dead time must be minimised, not padded.
GaN devices show \(R_{DS(on)}\) that depends on recent blocking-voltage history — charge trapping in the buffer that releases slowly. Static curve-tracer data will not reveal it; only switching-condition measurement will.
By the time a die is in a package and the package is on a board, the switching waveform belongs as much to the layout as to the silicon. Faster devices did not remove this problem; they made it the dominant one.
For a clamped inductive load — the standard hard-switching case, and what a double-pulse test reproduces — the switching energies are the overlap integrals of the transition, and the loss is what the heatsink has to remove:
The parasitics then set what those integrals actually look like:
The first term is why a 1200 V device gets specified for a 600 V bus. The second is the ringing frequency your EMI filter has to live with. The third is common-source feedback: \(L_s\) sits in the power loop and the gate loop simultaneously, so drain current slows its own turn-on — the reason a Kelvin source pin exists.
A fast \(dv/dt\) on the off device capacitively divides across \(C_{gd}\) and \(C_{gs}\). Parasitic turn-on follows whenever
Negative gate bias, a low-impedance off-state path, or an active Miller clamp are the three usual answers.
Junction-to-case resistance is only the first term. Solder, substrate, baseplate and interface material each add a stage, and each has its own time constant — which is why a single \(R_{th}\) cannot predict junction temperature under a real mission profile and a Foster or Cauer ladder can.
Package geometry also fixes clearance, creepage and partial-discharge inception. For SiC at 1200 V and above these frequently constrain the layout before the electrical parasitics do.
Further reading — R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics, ch. 4 (switch realization) and B. J. Baliga, Fundamentals of Power Semiconductor Devices. On this site: static characterisation · gate charge, capacitance & dynamic resistance · double-pulse testing · transient thermal impedance · characterisation guide.
None of the numbers above can be taken on trust. Everything on this page is only useful once it has been measured on the actual part, under stated conditions, on equipment built for the job.
Panxin Technology is our characterisation partner for power semiconductors. Their electrical and thermal test platforms produce the static curves, double-pulse waveforms, capacitance and gate-charge data, and transient thermal impedance measurements that sit behind our device models and the transistor database.
Splitting the work this way keeps the boundary honest: they measure, we model, and every parameter we publish can be traced back to a test with its conditions attached.
Everything on this page, stored per part as curves rather than headline numbers — SiC, GaN and IGBT specifications, switching waveforms, capacitance curves and thermal networks, built for automated device selection and mission-profile-aware design.
